1. Field of the Invention
The present invention relates to a logic circuit testing apparatus which can implement a scan-in/scan-out operation.
2. Description of the Prior Art
FIG. 1 shows an example of the prior art logic circuit testing apparatus which can implement a scan-in/scan-out operation. This testing apparatus has four parallel shiftpaths in each of which a plurality of shift registers (hereunder abbreviated to "SRL"s) 1 are linked together in a line. In this figure, the internal circuit arrangement of each of the shift-paths or scan-paths 26, 27 and 28 is the same as that of the shift-path 25 and, thus, the specific circuits are omitted in blocks 26, 27 and 28. Further, this logic circuit testing apparatus has two terminals 3a and 3b each connected to both a decoder 4 and a multiplexer 5. These terminals 3a and 3b receive input signals each indicating which one of the shift paths 25, 26, 27 and 28 is to be used for implementing a scan-in/scan-out operation. The decoder 4 is used to select a path out of the paths 25, 26, 27 and 28 to which "scan-in data" is to be provided from a "scan-in terminal" 6 Further, the multiplexer 5 is used to choose a path among the paths 25, 26, 27 and 28 from which data is provided to a "scan-out terminal" A clock signal causing a shifting operation of the SRL 1 is inputted from the "clock terminal" 9 and transmitted only to the shift-path selected by the decoder 4 through an AND circuit 8. Furthermore, the apparatus of FIG. 1 is provided with a mode switching terminal 10 for receiving a signal indicating a normal mode in which the SRLs 1 normally operate, or another signal indicating a scan mode in which the shift-path operates to set a certain logical value in the SRLs 1.
FIG. 2 shows an example of internal structure of a SRL 1 which is a composing element of the shift-path or scan-path shown in FIG. 1. Reference numeral 101 indicates a common or ordinary flip-flop which is used to fetch and hold data and output the data held by it. Reference numerals 102 and 103 represent N-channel transmission gates (hereinafter abbreviated to "N ch T G"). Further, reference numeral 104 indicates an inverter circuit for taking a logical inversion of a signal received from the mode switching terminal 10. Moreover, reference numeral 105 indicates an input terminal (not shown in FIG. 1) of the flip-flop 101 being in the normal mode and is provided independently to each of the SRLs 1. Reference numerals 13 and 14 represent an input terminal and an output terminal of the flip-flop 101 being in the scan mode, respectively.
The prior art logical circuit testing apparatus which can implement the scan-in/scan-out operation is constructed as above stated.
In case of putting the testing apparatus into the scan mode and activating the shift-path, a signal of high-level "H" is inputted at the mode switching terminal 10. Thus, the signal of high-level "H" is inputted at the gate electrode so that the "N ch T G" 102 turns on. On the other hand, the "N ch T G" 103 turns off because the gate electrode receives a signal of low-level "L" through the inverter 104. This results in the terminal 13 being selected as an input terminal of the flip-flop 101 and the SRLs 1 being connected with each other like a chain so as to make a shift-path. When a "scan-in" operation is implemented to set a logical value in the SRLs 1, signals indicating a certain shift-path to be put the logical value thereinto is first inputted from the terminals 3a and 3b. The signals inputted from the terminals 3a and 3b then goes into the decoder 4 and are decoded therein. The decoder 4 outputs a signal of high-level "H" only to an AND circuit 8 placed at a stage preceding to a desired shift-path and a signal of low-level "L" to the other AND circuits 8. Thus, the clock signal from the terminal 9 is transmitted by way of the AND circuit 8 only to the desired shift-path. The "scan-in data" is inputted from the terminal 6 to the desired shift-path with varying in synchronism with the clock signal and is set in the shift-path from the SRL 1 positioned at the last stage of the desired shift-path to the SRL 1 positioned at the first stage (from left, as viewed in FIG. 1) thereof in that order of the SRL 1. When the number of the stages or SRLs in the desired shift-path times a period of time of the clock signal is passed, it finishes setting the logical values in all of the SRLs 1 of the desired shift-path. Further, in case of setting logical values in the other shift-paths, the desired shift-path is first indicated by signals inputted at the terminals 3a and 3b and further the procedures as above described are to be effected. On the other hand, when a "scan-out" operation is implemented to read out the logical value held in the SRLs 1, the shift-path holding the logical value to be read therefrom is indicated by signals inputted from the terminals 3a and 3b. As in the case of the "scan-in" operation as above described, the clock pulse is transmitted thorough the decoder 4 and the AND circuit 8 only to the indicated shift-path. Moreover, the signals from the terminals 3a and 3b are also inputted to the multiplexer 5 for indicating which of the shift-paths outputs "scan-out data" to the terminal 6. The SRLs 1 placed from the last stage to the first stage of the indicated shift-path output the scan-out data in that order. At the point of time when the number of the stages or SRLs of the indicated shiftpath times a period of time of the clock signal is passed since the beginning of the "scan-out" operation, the readout operation of the logic values held in all the SRLs is completed.
Next, in case of setting the testing apparatus in the normal mode in which each of the SRLs 1 normally operates, a signal of low-level "L" is inputted at the terminal 10. Thus, a signal of low-level "L" is inputted to the gate or electrode so that the "N ch T G" 102 turns off. Conversely, a signal of high-level "H" is inputted through the inverter circuit 104 and thus the "N ch T G" 103 turns on. Thus, the terminal 105 is selected as an input terminal of the flip-flop 101 and accordingly the SRLs 1 are independent of each other and operate in the normal manner.
The prior art logical circuit testing apparatus is constructed as above described and the direction of shifting the logical value held in each SRL of a shift-path is fixed. Therefore, the prior art testing apparatus has a drawback in that if a failure occurs in some of the SRLs of the shift-path, the shift-path in question cannot operate and consequently the failing SRL cannot be located.
The present invention is accomplished to solve the above described problems of the prior art logical circuit testing apparatus.